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m41t00cap serial access real - time clock (rtc) with integral backup battery and crystal datasheet - production data features ? real - time clock (rtc) with backup battery integrated into package ? uses m41t00s enhanced rtc with precision switchover reference ? 400 khz i 2 c serial interface ? automatic switchover and deselect circuitry with fixed reference voltage ? v cc = 2.7 to 5.5 v operating voltage range ? 2.6 v (typ) power - fail deselect (switchover) threshold ? counters for seconds, minutes, hours, day, date, month, year and century ? software clock calibration ? low operating current of 300 a ? oscillator stop detection ? battery backup ? operating temperature of 0 to 70 c ? self - contained battery and crys tal in caphat? dip package ? rohs compliant ? lead- free second level interconnect description the m41t00cap is a low - power serial real - time clock (rtc) with integral battery and c rystal in st?s 24 - pin caphat? package. it includes a crystal controlled, 32.768 khz oscillator and has a built - in power sense circuit which detects power failures and automatically switches to the backup battery when a power failure occurs. eight registers comprise the clock/calendar function and are configured in binary - coded decimal (bcd) format. addresses and data are transferred serially via an industry standard, two line, 400 khz, bidirectional i 2 c interface. the built - in address register is incremente d automatically after each write or read data byte. the internal lithium coin cell contains ample energy to sustain timekeeping operation for 10 years in the absence of system power. the eight clock address locations contain the century, year, month, date, day, hour, minute, and second in 24- hour bcd format. corrections for the number of days in a month, including leap year, are made automatically (leap year valid up to year 2100). 24 1 pcdip24 battery/crystal caph a t? october 2014 docid014557 rev 6 1 / 24 this is information on a product in full production. www.st.com
contents m41t00cap conte nts 1 overview .......................................................................................... 5 1.1 pin connections ................................................................................. 6 1.2 pin description ................................................................................... 6 2 operatio n ......................................................................................... 7 2.1 wire bus characteristics .................................................................... 7 2.2 bus not busy ..................................................................................... 7 2.3 start da ta transfer ............................................................................. 7 2.4 stop data transfer .............................................................................. 7 2.5 data valid .......................................................................................... 8 2.6 acknowledge ..................................................................................... 8 2.7 read mode ...................................................................................... 9 2.8 write mode ................................................................................... 11 2.9 data retention mode ........................................................................ 11 3 clock operation ............................................................................. 12 3.1 clock registers ................................................................................ 13 3.2 calibrating the clock ........................................................................ 13 3.3 century bit ....................................................................................... 14 3.4 oscillator fail detection .................................................................... 15 3.5 output driver pin .............................................................................. 15 3.6 initial power - on default .................................................................... 15 4 maximum ratings ........................................................................... 16 5 dc and a c parameters ................................................................. 17 6 package information ..................................................................... 20 6.1 pcdip24 package ........................................................................... 20 7 part n umbering .............................................................................. 21 8 environmental information ........................................................... 22 9 revision history ............................................................................ 23 2 / 24 docid014557 rev 6
m41t00cap list of tables list of tables table 1: pin description .............................................................................................................................. 6 table 2: timekeeper? register map ..................................................................................................... 12 table 3: preferred default values .............................................................................................................. 15 table 4: absolute maximum ratings ......................................................................................................... 16 table 5: operating and ac measurement conditions ............................................................................... 17 table 6: capacitance ................................................................................................................................ 17 table 7: dc characteristics ....................................................................................................................... 18 table 8: power down/up ac characteristics ............................................................................................. 18 table 9: power down/up trip points dc characteristics ............................................................................ 19 table 10: ac characteristics ..................................................................................................................... 19 table 11: pcdip24 ? 24- pin plastic dip, battery caphat?, package mechanical data ....................... 20 table 12: document revision history ........................................................................................................ 23 docid014557 rev 6 3 / 24
list of figures m41t00cap list of figures figure 1: logic diagram .............................................................................................................................. 5 figure 2: block diagram .............................................................................................................................. 5 figure 3: dip connections .......................................................................................................................... 6 figure 4: serial bus data transfer sequence ............................................................................................... 8 figure 5: acknowledgement sequence ....................................................................................................... 9 figure 6: slave address location ................................................................................................................ 9 figure 7: read mode sequence .............................................................................................................. 10 figure 8: alte rnative read mode sequence ............................................................................................ 10 figure 9: write mode sequence ............................................................................................................ 11 figure 10: crystal acccuracy across temperature .................................................................................... 14 figure 11: clock calibration ...................................................................................................................... 14 figure 12: ac measurement i/o waveform .............................................................................................. 17 figure 13: power - down/up mode ac waveforms ..................................................................................... 18 figure 14: bus timing requirements sequence ......................................................................................... 19 figure 15: pcdip24 - 24 - pin plastic dip, battery cap hat?, package outline ...................................... 20 figure 16: ordering information scheme .................................................................................................. 21 figure 17: recycling symbols ................................................................................................................... 22 4 / 24 docid014557 rev 6
m41t00cap overview 1 overview figure 1 : logic diagram figure 2 : block diagram scl v c c m41t00 c ap v ss s d a ft/out ai09165 rea l time clock calen d ar r tc calibr a tion fre uenc y tes t oscil l a t or f ai l circui t logic outpu t ft/ou t (1) interna l p o wer f t ou t s d a sc l v cc com p are i 2 c inter f a ce 32kh oscil l a t or v b a t c r ys t a l v so v pfd ai09168 write p r o tec t dcid014557 re 6 5 / 24
overview m41t00cap 1.1 pin connections figure 3 : dip connections 1. du is "don't use". do not connect. must be allowed to float. do not connect to v cc or v ss . 1.2 pin description table 1: pin description symbol name and function ft/out frequency test / output driver (open drain) sda serial data input/output scl serial clock input v cc supply voltage v ss ground du (1) do not use. do not connect. reserved for factory use. nc no connection notes: (1) du is ?don?t use?. do not connect. must be allowed to float. do not connect to v cc or v ss . nc nc nc nc nc nc nc nc nc nc ft/out nc nc nc nc nc scl nc nc du v ss s d a nc v c c ai01028 m41t00 c ap 8 1 2 3 4 5 6 7 9 10 11 12 16 15 24 23 22 21 20 19 18 17 14 13 (1) 6 / 24 dcid014557 re 6
m41t00cap operation 2 operation the m41t00cap clock operates as a slave device on the i 2 c serial bus. access is obtained by implementing a start condition followed by the correct slave address (d0h). the 8 byt es contained in the device can then be accessed sequentially in the following order: 1. seconds register 2. minutes register 3. century/hours register 4. day register 5. date register 6. month register 7. year register 8. calibration register the m41t00cap clock continual ly monitors v cc for an out - of - tolerance condition. should v cc fall below v pfd , the device terminates an access in progress and resets the device address counter. inputs to the device will not be recognized at this time to prevent erroneous data from being written to the device from a an out - of - tolerance system. once v cc falls below the switchover voltage (v so ), the device automatically switches over to the battery and powers down into an ultra - low current mode of operation to prolong battery life. if v bat i s less than v pfd , the device power is switched from v cc to v bat when v cc drops below v bat . if v bat is greater than v pfd , the device power is switched from v cc to v bat when v cc drops below v pfd . upon power - up, the device switches from battery to v cc at v so . when v cc rises above v pfd , the inputs will be recognized. for more information on battery storage life refer to application note an1012. 2.1 wire bus characteristics the bus is intended for communication between different ics. it consists of two lines: a bidirectional data signal (sda) and a clock signal (scl). both the sda and scl lines must be connected to a positive supply voltage via a pull - up resistor. the following protocol has been defined: ? data transfer may be initiated only when the bus is not busy. ? during data transfer, the data line must remain stable whenever the clock line is high. ? changes in the data line, while the clock line is high, will be interpreted as control signals. accordingly, the following bus conditions have been defined: 2.2 bus not busy b oth data and clock lines remain high. 2.3 start data transfer a change in the state of the data line, from high to low, while the clock is high, defines the start condit ion. 2.4 stop data transfer a change in the state of the data line, from low to high, while the clock is high, defines the stop condition. docid014557 rev 6 7 / 24
operation m41t00cap 2.5 data valid the state of the data line represents valid data when after a start condition, the data line is stable for the duration of the high period of the clock signal. the data on the line may be change d during the low period of the clock signal. there is one clock pulse per bit of data. each data transfer is initiated with a start condition and terminated with a stop condition. the number of data bytes transferred between the start and stop conditions i s not limited. the information is transmitted byte - wide and each receiver acknowledges with a ninth bit. by definition a device that gives out a message is called ?transmitter,? the receiving device that gets the message is called ?receiver.? the device th at controls the message is called ?master.? the devices that are controlled by the master are called ?slaves.? 2.6 acknowledge each byte of eight bits is followed by one acknowl edge bit. this acknowledge bit is a low level put on the bus by the receiver whereas the master generates an extra acknowledge related clock pulse. a slave receiver which is addressed is obliged to generate an acknowledge after the reception of each byte t hat has been clocked out of the master transmitter. the device that acknowledges has to pull down the sda line during the acknowledge clock pulse in such a way that the sda line is a stable low during the high period of the acknowledge related clock pulse. of course, setup and hold times must be taken into account. a master receiver must signal an end of data to the slave transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. in this case the transmitter must l eave the data line high to enable the master to generate the stop condition. figure 4 : serial bus data transfer sequence 8 / 24 docid014557 rev 6 ai00587 d a t a clock d a t a line s t able d a t a v alid s t a r t condition change of d a t a al l o wed s t o p condition
m41t00cap operation figure 5 : acknowledgement sequence 2.7 read mode in this mode the master reads the m41t00cap slave after setting the slave address (see figure 7: "read mode sequence" ). following the write mode control bit (r/w = 0) and the ac knowledge bit, the word address 'an' is written to the on - chip address pointer. next the start condition and slave address are repeated followed by the read mode control bit (r/w = 1). at this point the master transmitter becomes the master receiver. the d ata byte which was addressed will be transmitted and the master receiver will send an acknowledge bit to the slave transmitter. the address pointer is only incremented on reception of an acknowledge clock. the m41t00cap slave transmitter will now place the data byte at address an+1 on the bus, the master receiver reads and acknowledges the new byte and the address pointer is incremented to ?an+2.? this cycle of reading consecutive addresses will continue until the master receiver sends a stop condition to t he slave transmitter. the system - to - user transfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). the updating will resume upon a stop condition or when the pointer increments to any non - clock address (07h). this is true both in read mode and write mode. an alternate read mode may also be implemented whereby the master reads the m41t00s slave without first writing to the (volatile) address pointer. the first address that is read is the last one stored in the pointer (see fi gure 8: "alternative read mode sequence" ). figure 6 : slave address location ai00601 d a t a output b y receiver d a t a output b y t r ansmi t ter scl f r om m aster s t a r t c l ock pulse for a cknowledgement 1 2 8 9 msb lsb ai00602 r/w sl a ve address s t a r t a 0 1 0 0 0 1 1 msb lsb dcid014557 re 6 9 / 24
operation m41t00cap figure 7 : read mode sequence figure 8 : alternative read mode sequence ai00899 bus activit y : ack s ack ack ack no ack s t o p s t a rt p sd a line bus activit y : master r/w d at a n d at a n+1 d at a n+x word address (an) sl a ve address s s t a rt r/w sl a ve address ack ai00895 bus a c tivi t y : a ck s a ck a ck a ck no a ck s t op s t a r t p s d a line bus a c tivi t y : m aster r/w d a t a n d a t a n+1 d a t a n+x sl a ve address 10/ 24 docid014557 rev 6
m41t00cap operation 2.9 write mode in this mode the master transmitter transmits to the m41t00cap slave receiver. bus protocol is shown in figure 9: "write mode sequence" . following the star t condition and slave address, a logic '0' (r/w=0) is placed on the bus and indicates to the addressed device that word address ?an? will follow and is to be written to the on - chip address pointer. the data word to be written to the memory is strobed in ne xt and the internal address pointer is incremented to the next address location on the reception of an acknowledge clock. the device slave receiver will send an acknowledge clock to the master transmitter after it has received the slave address and again a fter it has received the word address and after each data byte. figure 9 : write mode sequence 2.10 data retention mode with valid v cc applied, the m41t00cap can be accessed as described above with read or write cycles. should the supply voltage decay, the power input will be switched from the v cc pin to the battery when v cc falls below the battery backup switchover voltage (v so ). at thi s time the clock registers will be maintained by the internal battery supply. on power - up, when v cc returns to a nominal value, write protection continues for t rec after v cc rises above v so . ai00591 bus a c tivi t y : a ck s a ck a ck a ck a ck s t op s t a r t p s d a line bus a c tivi t y : m aster r/w d a t a n d a t a n+1 d a t a n+x word address ( a n) sl a ve address dcid014557 re 6 11/ 24
clock operation m41t00cap 3 clock operation the 8 - byte register map (see table 2: "timekeeper? register map" ) is used to both set the clock and to read the date and time from the clock, in a binary coded decimal format. seconds, minutes, and hours are contained within the first three registers. bits d6 and d7 of clock register 02h (century/hours register) contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. bits d0 through d2 of register 03h contain the day (day of week). registers 04h, 05h, and 06h contain the date (day of month) , month and years. the eighth clock register is the calibration register (this is described in the clock calibration section). bit d7 of register 00h contains the stop bit (st). setting this bit to a '1' will cause the oscillator to stop. if the device is expected to spend a significant amount of time on the shelf, the oscillator may be stopped to reduce current drain. when reset to a '0' the oscillator restarts within one second. the seven clock registers may be read one byte at a time, or in a sequential block. the calibration register (address location 07h) may be accessed independently. provision has been made to ensure that a clock update does not occur while any of the seven clock addresses are being read. if a clock address is being read, an update of the clock registers will be halted. this will prevent a transition of data during the read. table 2: timekeeper ? register map addr function/range bcd format d7 d6 d5 d4 d3 d2 d1 d0 00h st 10 seconds seconds seconds 00-59 01h of 10 minutes minutes minutes 00-59 02h ceb cb 10 hours hours (24 - hour format) century/hours 0 - 1/00- 23 03h 0 0 0 0 0 day of week day 01-7 04h 0 0 10 date date: day of month date 01-31 05h 0 0 0 10m month month 01-12 06h 10 years year year 00-99 07h out ft s calibration calibration keys: 0 = must be set to '0' cb = century bit ceb = century enable bit ft = frequency test bit of = oscillator fail bit out = output level s = sign bit st = stop bit 12/ 24 docid014557 rev 6
m41t00cap clock operati on 3.1 clock registers the m41t00cap has 8 internal registers which contain clock and calibration data. these registers are memory locations which contain external (user accessible) and intern al copies of the data (usually referred to as biport? timekeeper cells). the external copies are independent of internal functions except that they are updated periodically by the simultaneous transfer of the incremented internal copy. the system - to - user t ransfer of clock data will be halted whenever the address being read is a clock address (00h to 06h). the update will resume either due to a stop condition or when the pointer increments to any non - clock address (07h). clock registers store data in bcd. th e calibration register stores data in binary format. the internal divider (or clock) chain will be reset upon the completion of a write to any clock address. 3.2 calibrating the clock the m41t00cap is driven by a quartz - controlled oscillator with a nominal frequency of 32,768 hz. the devices are tested not to exceed 23 ppm (parts per million) oscillator frequency error at 25c, which equates to about 1 minute per mont h (see figure 10: "crystal acccuracy across temperature" ). when the calibration circuit is properly employed, accuracy improves to better than 2 ppm at 25c. the oscillation rate of crystals changes with temperature. the m 41t00cap design employs periodic counter correction. the calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in figure 11: "clock calibration" . the number of times pulses which are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five calibration bits found in the calibration register. adding counts speeds the clock up, subtracting counts slows the clock down. the calibration bits occupy the five lower order bits (d4 - d0) in the calibration register 07h. these bits can be set to represent any value between 0 and 31 in binary form. bit d5 is a sign bit; '1' indicates positive calibration, '0' indicates negative calibration. calibration occurs within a 64 minute cycle. the first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. if a binary '1' is loaded into the registe r, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or ? 2.034 ppm of adjustment per calibration step in the calibration register (see figure 11: "clock calibration" ). assuming that the oscillator is running at exactly 32,768 hz, each of the 31 increments in the calibration byte would represent +10.7 or ? 5.35 seconds per month which corresponds to a total possible adjustment range of +5.5 or ? 2.75 minutes per month. two methods are available for ascertaining how much calibration a give n m41t00cap may require. the first involves setting the clock, letting it run for a month and comparing it to a known accurate reference and recording deviation over a fixed period of time. calibration values, including the number of seconds lost or gained in a given period, can be found in application note an934, ?timekeeper ? calibration.? this allows the designer to give the end user the ability to calibrate the clock as the environment requires, even if the final product is packaged in a non - user service able enclosure. the designer could provide a simple utility that accesses the calibration byte. the second approach is better suited to a manufacturing environment, and involves the use of the ft/out pin. the pin will toggle at 512 hz, when the stop bit (s t, d7 of 00h) is '0,' and the frequency test bit (ft, d6 of 07h) is '1.' any deviation from 512 hz indicates the degree and direction of oscillator frequency shift at the test temperature. for example, a reading of 512.010124 hz would indicate a +20 ppm os cillator frequency error, requiring a ? 10 (xx001010) to be loaded into the calibration byte for correction. note that setting or changing the calibration byte does not affect the frequency test output frequency. the ft/out pin is an open drain output which docid014557 rev 6 13/ 24
clock operation m41t00cap requires a pull - up resistor to v cc for proper operation. a 500 - 10 kw resistor is recommended in order to control the rise time. the ft bit is cleared on power - down. figure 10 : crystal acccuracy across temperature figure 11 : clock calibration 3.3 century bit bits d7 and d6 of clock register 02h contain the century enable bit (ceb) and the century bit (cb). setting ceb to a '1' will cause cb to toggle, either from a '0' to '1' or from '1' to '0' at the turn of the century (depending upon its initial state). if ceb is set to a '0,' cb will not toggle. ai07888 C160 0 10 20 30 40 50 60 70 f r equen c y (ppm) t empe r a tu r e c 80 C10 C20 C30 C40 C100 C120 C140 C40 C60 C80 20 0 C20 = C0.036 ppm/ c 2 0.006 ppm/ c 2 k ? f = k x ( t C t o ) 2 f t o = 25 c 5 c ai00594b nor m al positive c alib r a tion neg a tive c alib r a tion 14/ 24 docid014557 rev 6
m41t00cap clock operation 3.5 oscillator fail detection if the oscillator fail bit (of) is internally set to '1,' this indicates that the oscillator has either stopped, or was stopped for some period of time and can be used to judge the validity of the clock and date data. in the event the of bit is found to be set to '1' at any time other than the initial power - up, the stop bit (st) should be written to a '1,' then immediately reset to '0.' this will restart the oscillator. the following conditions can cause the of bit to be set: ? the first time power is applied (defaults to a '1' on power - up). ? the voltage present on v cc is insufficient to support oscillation. ? the st bit is set to '1'. ? external interference of the crystal. the of bit will remain set to '1' until written to logic '0.' the oscillator must have started and run for at least 4 seconds before attempting to reset the of bit to '0.' 3.6 output driver pin when the ft bit is not set, the ft/out pin becomes an output driver that reflects the contents of d7 of the calibration register. in other words, when d7 (out bit) and d6 (ft bit) of address location 07h are '0's, then the ft/out pin will be driven low. the ft/out pin is an open drain which requires an external pull - up resistor. 3.7 initial power - on default upon initial application of powe r to the device, the out and ft bits will be in the '0' state, and the st and of bits will be in the '1' state. all other register bits will initially power on in random states (see table 3: "preferred default values" ). table 3: preferred default values condition st out ft of initial power -up (1) 1 0 0 1 subsequent power - up (with battery backup) (2) uc uc 0 uc notes: (1) state of other control bits undefined. (2) uc = unchanged docid014557 rev 6 15/ 24
maximum ratings m41t00cap 4 maximum ratings stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 4: absolute maximum ratings sym parameter value unit t stg storage temperature (v cc off, oscillator off) ? 55 to 125 c v cc supply voltage ? 0.3 to 7 v t sld (1) (2) lead solder temperature for 10 seconds 260 c v io input or output voltages ? 0.3 to v cc +0.3 v i o output current 20 ma p d power dissipation 1 w notes: (1) for dip packaged devices, ultrasonic vibrations should not be used for post - solder cleaning to avoid damaging the crystal. (2) soldering temperature of the ic leads is to not exceed 260 c for 10 seconds. in order to protect the lithium battery, preheat temperatures must be limited such that the battery temperature does not exceed +85 c. furthermor e, the devices shall not be exposed to ir reflow. negative undershoots below ? 0.3 volts are not allowed on any pin while in the battery backup mode. 16/ 24 docid014557 rev 6
m41t00cap dc and ac parameters 5 dc and ac parameters this section summarizes the operating and measurement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac ch aracteristic tables are derived from tests performed under the measurement conditions listed in table 5: "operating and ac measurement conditions" . designers should check that the operating conditions in their projects matc h the measurement conditions when using the quoted parameters. table 5: operating and ac measurement conditions parameter m41t00cap supply voltage (v cc ) 2.7 to 5.5 v ambient operating temperature (t a ) 0 to 70 c load capacitance (c l ) 100 pf input rise and fall times 5 ns input pulse voltages 0.2 v cc to 0.8 v cc input and output timing ref. voltages 0.3 v cc to 0.7 v cc output hi - z is defined as the point where data is no longer driven. figure 12 : ac measurement i/o waveform table 6: capacitance symbol parameter (1) (2) min max unit c in input capacitance - 7 pf c out (3) output capacitance - 10 pf t lp low - pass filter input time constant (sda and scl) - 50 ns notes: (1) at 25 c, f = 1 mhz. (2) effective capacitance measured with power supply at 5 v; sampled only, not 100% tested. (3) outputs deselected. ai02568 0.8v c c 0.2v c c 0.7v c c 0.3v c c docid014557 rev 6 17/ 24
dc and ac parameters m41t00cap table 7: dc characteristics sym parameter test condition (1) min typ max uni t i li input leakage current 0 v v in v cc - 1 a i lo output leakage current 0 v v out v cc - 1 a i cc1 supply current switch freq = 400 khz - 300 a i cc2 supply current (standby) scl = 0 hz all inputs v cc ? 0.2 v v ss + 0.2 v - 70 a v il input low voltage ? 0.3 - 0.3 v cc v v ih input high voltage 0.7 v cc - v cc + 0.3 v v ol output low voltage i ol = 3.0 ma - 0.4 v output low voltage (2) (open drain) i ol = 10 ma - 0.4 v pull - up supply voltage (open drain) (2) - 5.5 v notes: (1) valid for ambient operating temperature: t a = 0 to 70 c; v cc = 2.7 to 5.5 v (except where noted). (2) for ft/out pin (open drain). figure 13 : power - down/up mode ac waveforms table 8: power down/up ac characteristics symbol parameter (1) (2) min typ max unit t pd scl and sda at v ih before power down 0 - - ns t rec scl and sda at v ih after power up 10 - - s notes: (1) valid for ambient operating temperature: t a = 0 to 70 c; v cc = 2.7 to 5.5 v (except where noted). (2) v cc fall time should not exceed 5 mv/s. ai00596 v cc trec tpd v so sda scl don't care 18/ 24 docid014557 rev 6
m41t00cap dc and ac parameters table 9: power down/up trip points dc characteristics sym parameter (1) (2) min typ max unit v pfd power - fail deselect 2.5 2.6 2.7 v hysteresis 25 mv v so battery backup switchover voltage v bat < v pfd v bat v v bat > v pfd v pfd v hysteresis 40 mv t dr (3) expected data retention time 10 years notes: (1) valid for ambient operating temperature: t a = ? 40 to 85 c; v cc = 2.7 to 5.5 v (except where noted). (2) all voltages referenced to v ss . (3) t a = 25c, v cc = 0 v, oscillator on. figure 14 : bus timing requirements sequence table 10: ac characteristics sym parameter (1) min typ max units fscl scl clock frequency 0 - 400 khz tlow clock low period 1.3 - s thigh clock high period 600 - ns tr sda and scl rise time - 300 ns tf sda and scl fall time - 300 ns thd:sta start condition hold time (after this period the first clock pulse is generated) 600 - ns tsu:sta start condition setup time (only relevant for a repeated start condition) 600 - ns tsu:dat (2) data setup time 100 - ns thd:dat data hold time 0 - s tsu:sto stop condition setup time 600 - ns tbuf time the bus must be free before a new transmission can start 1.3 - s notes: (1) valid for ambient operating temperature: t a = 0 to 70 c; v cc = 2.7 to 5.5 v (except where noted). (2) transmitter must internally provide a hold time to bridge the undefined region (300 ns max) of the falling edge of scl. ai00589 s d a p tsu:s t o tsu:s t a thd:s t a sr scl tsu: d a t tf thd: d a t tr thigh tl o w thd:s t a t b uf s p dcid014557 re 6 19/ 24
package information m41t00cap 6 package information in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? speci fications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. 6.1 pcdip24 package figure 15 : pcdip24 - 24- pin plastic dip, battery caphat?, package outline drawing is not to scale. table 11: pcdip24 ? 24 - pin plastic dip, battery caphat?, package mechanical data symb mm inches typ min max typ min max a 8.89 9.65 0.350 0.380 a1 0.38 0.76 0.015 0.030 a2 8.38 8.89 0.330 0.350 b 0.38 0.53 0.015 0.021 b1 1.14 1.78 0.045 0.070 c 0.20 0.31 0.008 0.012 d 34.29 34.80 1.350 1.370 e 17.83 18.34 0.702 0.722 e1 2.29 2.79 0.090 0.110 ea 15.24 16.00 0.600 0.630 l 3.05 3.81 0.120 0.150 10 1 1650_j 20/ 24 docid014557 rev 6
m41t00cap part numbering 7 part numbering figure 16 : ordering information scheme 1 c p p a c 0 0 t 1 4 m : e l p m a x e d e v ice ty pe m4 1 t s u p p l y v o l t a g e and wri t e p r otect v o lt a g e 0 0 cap = v c c = 2 . 7 t o 5 . 5 v p a c k a g e pc = pcdip24 t e mp e r ature ran g e 1 = 0 c t o 7 0 c s h i p pi n g met h o d blan k = eco p a c k ? p a c kag e , tu b e s docid014557 rev 6 21/ 24
environmental information m41t00cap 8 environmental information figure 17 : recycling symbols this product contains a non - rechargeable lithium (lithium carbon monofluoride chemistry) button cell battery fully encapsulated in the final product. recycle or dispose of batteries in accordance with the battery manufacturer's instructions and local/national disposal and recycling regulations. 22/ 24 docid014557 rev 6
m41t00cap revision history 9 revision history table 12: document revision history date revision changes 28- jun - 2006 1 first release 20- mar -2008 2 document status upgraded to full datasheet; updated title and cover page, section "description" , section 2: "operation" , section 3: "clock operation" , figure 1: "logic diagram" , figure 2: "block diagram" , figure 3: "dip connectio ns" , figure 4: "serial bus data transfer sequence" , table 1: "pin description" , table 7: "dc characteristics" , table 8: "powe r down/up ac characteristics" , table 9: "power down/up trip points dc characteristics" , table 10: "ac characteristics" . 25- mar -2009 3 added section 8: "envi ronmental information" ; updated text in . 27- may -2010 4 updated section 4: "maximum ratings" , table 11: "pcdip24 ? 24- pin plastic dip, battery caphat?, package mechanical data" ; reformatted document. 22- mar -2012 5 updated title of document; section 8: "environmental information" . 28- oct - 2014 6 updated st and out bits in section 3.6: "init ial power - on default" updated section 6.1: "pcdip24 package" docid014557 rev 6 23/ 24
m41t00cap important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications , and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant information on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of or der acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and s t assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information se t forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2014 stmicroelectronics ? all rights reserved 24/ 24 docid014557 rev 6

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